The present invention relates to integrated circuit bond pads, and more particularly, to structures that allow for active circuitry to be formed under a bond pad.
Integrated circuits are formed from silicon wafers. After a wafer of circuits has been fabricated, the wafer is diced into individual die. Each die is mounted in an integrated circuit package. Packaged integrated circuits are typically mounted on circuit boards.
Integrated circuit die can be electrically connected to package pins using wire bonding techniques.
Each die has wire bond pads around its periphery. After a die has been mounted in an integrated circuit package, a wire bonding tool attaches wires between the wire bond pads on the die and the pins on the package. The bond pads and wires electrically connect the circuitry of the integrated circuit to the package pins, so that the circuitry can be used in a system.
The process by which the wires are attached to the bond pads and package pins is called wire bonding. Wire bonding tools typically form wire bonds using a combination of ultrasonic energy, heat, and pressure. A successful wire bond will remain reliable for many years.
One measure of wire bond quality is pull test performance. During a pull test, a wire bond is pulled to measure its strength. A bond exhibiting a poor pull test performance will not be reliable.
To address concerns about wire bond reliability, bond pad structures have been developed in which interconnect layers under each pad are patterned in a way that enhances the strength of the bond pad and any bond made to that pad. While these types of structures exhibit satisfactory pull test performance, they consume all of the real estate under the pad.
Modern circuits are becoming increasingly complex, which is forcing circuit designers to use circuit real estate as efficiently as possible. One possible way to use circuit real estate more efficiency is to use the area under the bond pads to form active circuits. Bond pads are fairly large, so significant efficiency gains can be realized by using the area under the pads for circuitry rather than for providing structural support for the pads.
Bond pad structures have been developed that free up some of the area under the pads for circuitry. In these structures, the uppermost interconnect layers are used to strengthen the pad, while the lower interconnect layers are left untouched. Because the lower interconnect layers under the pads are not used for structural support, they can be used for active circuitry.
Conventional bond pad structures of this type satisfy the need for additional circuit real estate, but are not always sufficiently robust. The interconnect layers in the dielectric stack under the pad can be fragile, which renders them susceptible to damage during the wire bonding process. Moreover, pad structures of this type sometimes exhibit unsatisfactory pull test performance. These problems can be particularly acute in integrated circuits with low-dielectric-constant dielectric stack materials and small bond pads.
It would therefore be desirable to be able to provide integrated circuit bond pad structures that accommodate under-pad circuitry while exhibiting improved structural qualities.